The present invention relates to a semiconductor memory apparatus, in particular which stores data by accumulating charges in its capacitor.
In a conventional semiconductor memory apparatus that stores data by accumulating charges in its capacitor, for example one disclosed in JP-A-2-3162, a memory cycle includes an active period and a non-active period. In this case, in the non-active period potentials in the pair of bit lines should be kept in balance and also should be precharged. In addition, the potential level of the precharge is set to one slightly lower than half of a power-supply potential Vcc depending on the characteristics (e.g., the threshold of potential) of a transistor to be used in a memory cell.
FIG. 3 is a signal waveform chart for illustrating the operation of the conventional semiconductor memory apparatus. In the figure, (a) represents signal waveforms of the respective bit lines BL, BL(bar) in the pair, and (b) represents a signal waveform of a word line WL. When the semiconductor memory apparatus is shifted into the non-active period, a precharge-instructing signal is brought into high. Then, a precharge-controlling circuit brings the pair of bit lines BL, BL(bar) into a conductive state to allow the bit lines BL, BL(bar) to be operated in balance. As shown in FIG. 3(a), the potential level of the pair of bit lines is Vccxc3x971/2, completing the balanced operation.
However, a voltage collector circuit lowers the final potential level of the pair of bit lines BL, BL(bar) by xcex94V1 from Vcc/2 for attaining the operation of the semiconductor memory apparatus at a low potential.
In the semiconductor memory apparatus having the dynamic-type memory cell described above, there is a great problem of how to realize a high-speed access. However, the above conventional apparatus requires a waiting time period xcex94t1 until the potential level of the pair of bit lines BL, BL(bar) is lowered to Vcc/2 and is further lowered by xcex94V1 after bringing the pair of bit lines BL, BL(bar) into a conductive state. Therefore, there is a problem in that the conventional semiconductor memory apparatus takes much time for attaining the operation at a low potential, resulting in a decrease in its processing speed.
For speeding up the processing speed, there is an idea of advancing the timing for bringing the pair of bit lines BL, BL(bar) into a conductive state. However, if the timing is advanced, the pair of bit lines BL, BL(bar) is brought into a conduction state in spite of insufficiently lowering the potential of the word line WL shown in FIG. 3(b). As a result, there is a possibility of causing a loss of data written in the memory cell. Therefore, it is impossible to advance the timing of bringing the pair of the bit lines BL, BL(bar) into conduction state.
Accordingly, the present invention has completed in consideration of the above facts. An object of the present invention is to provide a semiconductor memory apparatus that stores data by accumulating charges in its capacitor for allowing the operation thereof at a low potential and processing at a high speed.
For attaining the above object, in the first aspect of the present invention, a semiconductor memory apparatus for storing data by accumulating charges in a capacitor is provided, wherein before performing a precharge for bringing the potential of a pair of bit lines to an intermediate potential by making a short circuit in the pair of bit lines, the potential of the bit line being charged to a higher level is previously lowered to a level within the range that prevents data written in a memory cell from being disappeared.
In the second aspect of the present invention, a semiconductor memory apparatus for storing data by accumulating charges in a capacitor, comprises a forced step-down circuit comprised of a first switching element having one end connected to a driving line on the high side, and a forced step-down capacitor and a second switching element which are arranged in parallel between the other end of the first switching element and a ground potential, wherein the second switching element is brought into an on state in advance to hold the forced step-down capacitor at zero potential, and before performing a precharge for bringing the potential of a pair of bit lines to an intermediate potential by making a short circuit in the pair of bit lines, the first switching element is then brought into an on state and the potential of the driving line on the high side is previously lowered to a level within the range that prevents data written in a memory cell from being disappeared.